To smoothly display a moving image of a high frame rate.

A controller performs control of a frame memory so as to output an frame of a frame rate m as an output video signal S1, to output an +1 frame of the frame rate m as an output video signal S2 at the supply start time b delayed by 1/4m from the supply start time (a) of the frame, to output an +2 frame of the frame rate m as an output video signal S3 at the supply start time c delayed by 1/4m from the supply start time b of the +1 frame, and to output an +3 frame of the frame rate m as an output video signal S4 at the supply start time d delayed by 1/4m from the supply start time c of the +2 frame. The time period required to output each frame is 1/m and the cycle of outputting the head of each frame is nm Hz. This invention is applicable to an imaging device, an image signal processing device and an image display device.