To improve the flexibility of using form of an electronic device by constructing plural access flows to the 1st and 2nd DSPs (digital signal processors).
The image extension function board part 6 has a 1st interface circuit 60 which is connected an A-BUS 40 and a B-BUS 41 and also has a 2nd interface circuit 61. The circuit 61 is connected to the circuit 60 via a BUS 43 and a BUS 44. A 1st work memory 70 and a 1st DSP 80 are connected to the BUS 43, and a 2nd work memory 71 and a 2nd DSP 81 are connected to the BUS 44. Either of ABUS 40 and BBUS 41 can access the internal RAMs of both DSP 80 and 81 via the switching function of the circuit 60. Based on such constitutions of both circuits 60 and 61, various connection methods are available to the DSP 80 and 81 according to every using purpose.
SUZUKI MASAYUKI
MORIOKA SEISUKE
KURODA RYOJI
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