Title:
IMAGE MEMORY CONTROL DEVICE
Document Type and Number:
Japanese Patent JP3022405
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make executable the filtering of an image including resolution conversion without using a flipflop or a line buffer, by writing an input image line by line in sequence on N image memories, and simultaneously reading N lines from the image memories.
SOLUTION: A writing controller 10 generates the chip select signal selecting image memories 21-24 from the remainder of dividing the write vertical position wy by four and writes a continuous line on the image memories 21-24 in sequence from the value divided with the write vertical position wy by four. A reading controller 13 generates the excess divided with the read vertical position ry by four (selector signal 20), generates the value divided with the read vertical position ry by four, adds 0 or 1 to the value of a read base address signal generation section 15 based on the value of the selector signal 20, and distributes it to the image memories 21-24. The image memories 21-24 simultaneously output four continued lines.
Inventors:
Youichi Tamura
Application Number:
JP14549397A
Publication Date:
March 21, 2000
Filing Date:
June 03, 1997
Export Citation:
Assignee:
NEC
International Classes:
H04N5/907; G06T1/20; G06T5/20; G09G5/00; G09G5/36; H03M9/00; H04N5/14; (IPC1-7): G09G5/36; G06T1/00; G06T5/20; G09G5/00; H04N5/907
Domestic Patent References:
| JP6022878A | ||||
| JP6266831A | ||||
| JP7192125A |
Attorney, Agent or Firm:
Isamu Takahashi