PURPOSE: To allow the processing unit to have provision even in the case where image registers arranged in 3-rows and 3-columns except the center image register are arranged in point symmetry with the center image register so as to multiply an operator coefficient and to simplify the circuit configuration.

CONSTITUTION: Nine image registers L00-L22 are arranged in a matrix of 3-rows and 3-columns, image data are sequentially shifted from the image registers of an input side row 2a to an output side row 2b and stored and an operator coefficient is multiplied with the image data respectively for the space filtering processing. A sign inverter 11 inverting sign of the image data is provided between the image register L11 in the middle of the image registers arranged in 3-rows and 3-columns and the image register L01 adjacent to the image register L11 in the downstream in the shift direction. Furthermore, input adders S9-S12 adding the image data outputted from the image registers are provided to each of the image registers in pairs arranged in point symmetry around the image register L11 arranged in the middle.