To provide an image signal-processing device for achieving recoding with less image quality deterioration when recoding an image signal after processing.
When an image for synthesis processing is present in a cut block in a block synthesis circuit 58, the upper eight bits of an image signal at the side of a frame memory 51 and an image signal at the side of a synthesis signal generation circuit 53 (or the side of a synthesis signal input circuit 54) are inputted for synthesis processing, and the synthesized data are stored at a working memory 56. At the same time, in an Edited Flag insertion circuit 59, a bit at a specific position in data where the lower two bits are changed into blocks is rewritten to one and is stored at a working memory 57. In a deblock circuit 61, the upper eight bits and the lower two bits that are present in the working memories 56 and 57 after the synthesis are added to compose a 10-bit signal, which is written into the same position of the I frame memory 51.
ANDO ICHIRO
INOUE YASUO
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