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Patent Searching and Data


Title:
IMAGE SIGNAL TRANSMISSION SYSTEM, IMAGE SIGNAL ENCODER AND IMAGE SIGNAL DECODER
Document Type and Number:
Japanese Patent JPH06165147
Kind Code:
A
Abstract:

PURPOSE: To sharply reduce the size of a necessary memory device by continuously executing division and reconstitution in the horizontal and vertical directions.

CONSTITUTION: An input signal S31 is directly inputted to a high-order side dividing circuit 31 and a low-order side dividing circuit 32 in the horizontal direction. Outputs S32, S33 from the circuits 31, 32 are resampled at a half speed of an input signal transfer clock. Then thinned data outputted from the circuit 31 are horizontally stored in a memory 33. On the other hand, thinned data outputted from the circuit 32 are inputted to the succeeding high-order side and low-order side dividing circuits 34, 35 and horizontally divided and thinned data outputted from the circuit 34 are horizontally stored in the memory 33. Succeeding outputs from the circuit 32 are horizontally divided by repeating similar operation and divided components are stored in the memory 33. The horizontally divided components are vertically read out from the memory 33 and vertically divided into 4 components similarly to horizontal division. Finally the original data are two-dimensionally divided into 16 components.


Inventors:
KOJIMA YUICHI
Application Number:
JP30538192A
Publication Date:
June 10, 1994
Filing Date:
November 16, 1992
Export Citation:
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Assignee:
SONY CORP
International Classes:
H04N1/41; G06T9/00; H03M7/30; H03M7/40; H04N1/415; H04N19/126; H04N19/136; H04N19/14; H04N19/152; H04N19/176; H04N19/196; H04N19/423; H04N19/426; H04N19/46; H04N19/59; H04N19/60; H04N19/625; H04N19/635; H04N19/70; H04N19/85; H04N19/91; (IPC1-7): H04N7/133; G06F15/66; H03M7/30; H04N1/41; H04N1/415
Attorney, Agent or Firm:
Mitsuo Takahashi