Title:
IMPEDANCE ADJUSTMENT METHOD FOR MULTILAYER PRINTED CIRCUIT BOARD AND INTERLAYER LINE
Document Type and Number:
Japanese Patent JP2023044487
Kind Code:
A
Abstract:
To provide a technique to suppress signal degradation based on impedance mismatch caused by interlayer lines without sacrificing high-density mounting.SOLUTION: It has interlayer patterns 4. A plurality of pattern layers P1 to P8 is alternately stacked with a plurality of dielectric layers D1 to D7. Interstitial via holes 3 form interlayer lines that conduct the strip lines formed in each of the two different pattern layers. Gnd vias 4 are provided in parallel along the interlayer lines. Pattern layers P2 and P7, which are adjacent to pattern layers P3 and P6 across the dielectric layers D2 and D6, where the end patterns 31 of the interlayer lines are formed, have a non-patterned area 5 where the formation of conductor patterns is prohibited at the position opposite the end patterns 31.SELECTED DRAWING: Figure 1
Inventors:
ITO SHINTARO
SANADA KEI
YAZU ERIKO
SANADA KEI
YAZU ERIKO
Application Number:
JP2021152540A
Publication Date:
March 30, 2023
Filing Date:
September 17, 2021
Export Citation:
Assignee:
DENSO CORP
International Classes:
H05K3/46
Attorney, Agent or Firm:
Nagoya International Patent Attorney Corporation