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Patent Searching and Data


Title:
IMPEDANCE CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPS5487154
Kind Code:
A
Abstract:

PURPOSE: To reduce the level difference between input and output at the impedance conversion circuit, by inputting to the base of one transistor of the differential amplifying circuit and outputting after taking common the base and collector of another transistor.

CONSTITUTION: The base of TrQ1 of the differential amplifying circuit consisting of NPN transistors TrQ1,Q2 is taken as input and the base and collector of another TrQ2 are taken as output after being in common. To lower the output impedance and match the input and output level, the base and the collector of TrQ2 are connected and negative feedback is given. Further, to make complete this matching, TrQ1,Q2 are made to the same size, keeping equal to the base to emitter voltage characteristics, and the collector current is kept the same by making the same size for the constant current load PNP TrQ3 and Q4. Thus, the level difference between the input and output signals can be reduced.


Inventors:
TOJIKI HITOMI
Application Number:
JP15448377A
Publication Date:
July 11, 1979
Filing Date:
December 23, 1977
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03H11/40; H03H11/28; (IPC1-7): H03H7/38