Title:
IMPROVED EMITTER COUPLED TYPE LOGICAL CIRCUIT BIPOLAR MEMORYCELL
Document Type and Number:
Japanese Patent JPS61148866
Kind Code:
A
Abstract:
An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emmiter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.
Inventors:
MAMON TOOMASU
UEN SHII KOU
UEN SHII KOU
Application Number:
JP28685685A
Publication Date:
July 07, 1986
Filing Date:
December 17, 1985
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
G11C11/411; H01L21/74; H01L21/8222; H01L27/102; (IPC1-7): G11C11/40; G11C29/00; H01L27/10
Attorney, Agent or Firm:
Kuro Fukami