Title:
IMPROVED PROGRAMMABLE LOGIC CELL ARRAY ARCHITECTURE
Document Type and Number:
Japanese Patent JP3471088
Kind Code:
B2
Abstract:
PURPOSE: To obtain a PLCA architecture for efficiently supporting a demultiplexer (DEMUX) and a multiport register file(MPRF) without scarifying the function or flexibility of a PLCA.
CONSTITUTION: A conventional PLC architecture is corrected for executing a DEMUX by a single PLC operating in a backward direction. A reading/writing port for MPRF is executed by using each PLC functioning as a reading/writing port for one bit slice. When a PLC multiplexer 112 (constituted of a path transistor tree) operates in a backward direction for functioning as a DEMUX, a PLC memory 114 of a PLC 110 operates correction for transmitting a signal from the PLC multiplexer to the input of the PLC. A register file 119 is provided on the PLCA, and the MPRF is efficiently executed by correcting the PLC memories 114 and 130 or providing an OR circuit for a writing port so that the PLC can be operated in various modes (normal, forward, and backward directions). Each PLC is operated as a conventional PLC in the normal mode, a reading port in the forward mode, and a writing port in the backward mode. In this correction, it is hardly necessary to provide another circuit at a normally necessary circuit, and the number of the PLC necessary for the execution of the DEMUX or the MPRF can be sharply reduced.
Inventors:
Gregory S. Snyder
Application Number:
JP20317694A
Publication Date:
November 25, 2003
Filing Date:
August 29, 1994
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G11C11/41; G11C7/10; H01L21/82; H03K17/00; H03K19/173; (IPC1-7): H03K19/173; G11C11/41; H01L21/82; H03K17/00
Domestic Patent References:
| JP6318638A | ||||
| JP6291641A | ||||
| JP5122056A |
Attorney, Agent or Firm:
Kaoru Furuya (2 outside)