Title:
INCORPORATED SELF-TESTING CIRCUIT FOR MEMORY
Document Type and Number:
Japanese Patent JP3667146
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To dissolve a waiting time caused by insertion of a flip-flop and to decrease effectively the clock cycle time by generating an address of a test pattern, comparing output response of a memory device with expected memory response supplied by a delay buffer, and deciding whether a memory device is functioned normally or not.
SOLUTION: A BIST circuit is provided with a pattern generator, a BIST circuit output buffer (BOB), a delay buffer, and a comparator. The pattern generator is a limited state machine generating a series of test pattern, and corresponds to test algorithm. The BOB is a buffer between the BIST circuit and a memory device, and eliminates latent function reduction of a memory device caused by introduction of the BIST circuit. The delay buffer is a first-in- first-out(FIFO) register file between the pattern generator and the comparator.
Inventors:
Yellow tin Yu
quay fixed
quay fixed
Application Number:
JP9020699A
Publication Date:
July 06, 2005
Filing Date:
March 30, 1999
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing Company,Ltd.
International Classes:
G01R31/28; G06F11/22; G06F12/16; G11C29/00; G11C11/413; G11C29/12; H01L21/822; H01L27/04; (IPC1-7): G06F12/16; G01R31/28; G06F11/22
Domestic Patent References:
| JP10241399A |
Attorney, Agent or Firm:
Masatake Shiga
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama