Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3132451
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress generation of unevenness of application of a film to be formed through the application by forming a cutting line region of a second interlayer film inside the cutting line region of dummy wiring formed on an end part of a cutting line region of a first interlayer film.
SOLUTION: An interlayer film 115 is formed on the whole area of a semiconductor substrate 111, and a bit line 117 is formed to be connected to a contact 116 formed at a predetermined position, and dummy wiring 117a is formed at a predetermined position of an outer peripheral region 101 at the same time. Then, an interlayer film 118 is formed on the interlayer film 115 including the bit line 117 and the dummy wiring 117a, and dummy wiring 122a is disposed in the same layer with a cell plate 122 and inside from the dummy wiring 117a. Then, an interlayer film 123 is formed on the interlayer film 118 including the cell plate 122, and a resist pattern 124 is formed in a part to be a cutting region of the outer peripheral region 101, a peripheral circuit part 102, and the end part of the resist pattern 124 is located inside from the end part of the outer peripheral side of the dummy wiring 122a in the outer peripheral region 101.
Inventors:
Hideomi Shintaku
Application Number:
JP970698A
Publication Date:
February 05, 2001
Filing Date:
January 21, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L23/52; H01L21/301; H01L21/3205; H01L21/8242; H01L29/78; (IPC1-7): H01L21/3205; H01L21/301; H01L29/78
Attorney, Agent or Firm:
Masaki Yamakawa