Title:
【発明の名称】集積回路メモリ
Document Type and Number:
Japanese Patent JP2651957
Kind Code:
B2
Abstract:
An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.
Inventors:
KAARU ERU UON
REI CHAN
REI CHAN
Application Number:
JP41765890A
Publication Date:
September 10, 1997
Filing Date:
December 28, 1990
Export Citation:
Assignee:
MOTOROORA INC
International Classes:
G11C11/41; G11C7/10; G11C7/22; (IPC1-7): G11C11/41
Domestic Patent References:
| JP6453396A | ||||
| JP62214583A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi