Title:
【発明の名称】集積回路
Document Type and Number:
Japanese Patent JP2737005
Kind Code:
B2
Abstract:
The present invention is an EPLD device having an integrated read and programming row driver using CMOS technology. A shared node is coupled to activate output inverters which drive row word lines. During the read mode, another CMOS inverter, which is coupled to a read input line, controls the signal on the node for driving the output inverters. During the programming mode a plurality of programming transistors which are coupled in series to the shared node is activated by address signals to pull the shared node to a lower potential. The integrated read and programming row driver circuit combination reduces the physical size of the associated circuity used in the pitched constrained area.
Inventors:
SEODOA MARUDAA
RONARUDO DABURYU SUOOTSU
RONARUDO DABURYU SUOOTSU
Application Number:
JP17317889A
Publication Date:
April 08, 1998
Filing Date:
July 06, 1989
Export Citation:
Assignee:
INTERU CORP
International Classes:
G11C17/00; G11C16/06; G11C16/08; G11C16/10; (IPC1-7): G11C16/06
Attorney, Agent or Firm:
Masaki Yamakawa (3 outside)