PURPOSE: To provide a variable length decoder having a small circuit configuration appropriate for integration by specifying an address in a storage means by a partial bit of a variable length code.

CONSTITUTION: A variable length signal consisting of plural bits B0 to B10 is applied to a signal line L2, upper 6 bits B0 to B5 are applied to a bank selecting circuit 22 and all the bits B0 to B10 are applied to a bit selector 23. The circuit 22 generates a 2-bit bank selecting signal BSL in response to the 6 bits B0 to B5 and the generated signal BSL is applied to a table memory 21a as upper two bits A0, A1 and also is applied to the bit selector 23. The selector 23 selects five bits out of the 11 bits B0 to B10 in response to the signal BSL and applies the selected bits to the memory 21a as lower five bits A2 to A6. Banks BA0 to BA3 are selected by the upper two bits A0, A1 and code information whose address is specified by the lower five bits A2 to A5 is read out.