Title:
INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, AND PROGRAM
Document Type and Number:
Japanese Patent JP2014010549
Kind Code:
A
Abstract:
To omit a ROM for a CPU in an information processing apparatus having the CPU and an FPGA.
In an information processing apparatus having a CPU and an FPGA (Field Programmable Gate Array), by causing the FPGA to function as a ROM for the CPU instead of a ROM storing a boot program for the CPU at startup, separate preparation of storage media for the CPU and the FPGA is avoided, thereby omitting the ROM for storing the boot program for the CPU.
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Inventors:
ITO HIROKI
Application Number:
JP2012145659A
Publication Date:
January 20, 2014
Filing Date:
June 28, 2012
Export Citation:
Assignee:
CANON KK
International Classes:
G06F9/445
Domestic Patent References:
| JP2010251925A | 2010-11-04 | |||
| JP2000089949A | 2000-03-31 |
Foreign References:
| US20070208926A1 | 2007-09-06 |
Other References:
JPN6016015326; 山武一朗: '"特集 システム性能を引き出すメモリ活用＆設計法 第３章 ＣＰＵのプログラムとＦＰＧＡのコンフィグレー' Ｉｎｔｅｒｆａｃｅ 第３３巻，第３号（通巻３５７号）, 20070301, ｐｐ．６３-７６, ＣＱ出版株式会社
Attorney, Agent or Firm:
Takuma Abe
Sogo Kuroiwa
Sogo Kuroiwa