Title:
情報処理装置と負荷調停制御方法
Document Type and Number:
Japanese Patent JP5088371
Kind Code:
B2
Abstract:
An information processing device and a control method in a simultaneous multi-threading system qualitatively determine the load balance among the threads and arbitrate the performance load balance among threads. The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.
Inventors:
Takashi Suzuki
Toshio Yoshida
Toshio Yoshida
Application Number:
JP2009520148A
Publication Date:
December 05, 2012
Filing Date:
June 20, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/46; G06F9/48
Domestic Patent References:
| JP2006343872A | 2006-12-21 | |||
| JP2000020306A | 2000-01-21 | |||
| JP3714598B2 | 2005-11-09 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
virtue Tamio Ei
virtue Tamio Ei