To enhance the processing performance of a system LSI of multi-core structure.
The information processing device comprises the system LSI or a microprocessor including a plurality of CPU cores in one chip and a DRAM stacked thereon. In the system LSI chip, a chip multi-divided I/O distributed architecture is adopted. A plurality of independently operating CPU cores are provided in the system LSI. Each CPU core is provided with a 3D interface circuit, and independent data transmission/reception is allowed. In the DRAM chip, the chip multi-divided I/O distributed architecture is also adopted. The DRAM is divided into a plurality of independently operating DRAM cores. Each DRAM core is provided with a 3D interface circuit, and independent data transmission/reception is allowed.
TAKEMURA RIICHIRO
OSADA KENICHI
SAEN MAKOTO
MIURA SEISHI
KURODA YUKI
