Title:
情報処理装置
Document Type and Number:
Japanese Patent JP4247132
Kind Code:
B2
Abstract:
A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
Inventors:
Hirotsu Teppei
Yuichi Abe
Ken Kataoka
Yasuhiro Nakatsuka
Yuichi Abe
Ken Kataoka
Yasuhiro Nakatsuka
Application Number:
JP2004021207A
Publication Date:
April 02, 2009
Filing Date:
January 29, 2004
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F9/38; G06F9/48; G06F9/30; G06F9/32; G06F9/42; G06F9/46
Domestic Patent References:
| JP51046038A | ||||
| JP2001100996A | ||||
| JP8221270A | ||||
| JP3147022A | ||||
| JP3177926A | ||||
| JP2004038338A | ||||
| JP2000105715A | ||||
| JP2000181710A |
Attorney, Agent or Firm:
Yamato Tsutsui