Title:
情報処理装置、その制御方法およびプログラム
Document Type and Number:
Japanese Patent JP6584487
Kind Code:
B2
Abstract:
A verification circuit provided in an information processing apparatus verifies the presence or absence of the tampering of a boot program stored in a memory. A monitoring circuit monitors a signal communicated between the verification circuit and the memory and detects that the start-up of a system has failed due to the tampering of the boot program based on a monitoring result of the signal. Subsequently, the monitoring circuit provides notification of information related to a cause of failure of the start-up of the system.
Inventors:
Yo Kobayashi
Application Number:
JP2017243940A
Publication Date:
October 02, 2019
Filing Date:
December 20, 2017
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F11/07
Domestic Patent References:
| JP2014518428A | ||||
| JP6035733A |
Foreign References:
| US20130013905 | ||||
| US20160055332 |
Attorney, Agent or Firm:
Ryoichi Takaoka
Nao Oda
Nao Oda