Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP3373253
Kind Code:
B2
Abstract:
PURPOSE: To improve the reliability of a system by eliminating a contradiction due to a data discrepant with a main storage device if a cache is hit in test- and-set mode.
CONSTITUTION: A main storage controller 14 is provided with a start signal generating circuit 12 which delays a start indication to a CPU 10 by a specific time and a processor 3 accesses a semaphore bit setting part by test-and-set operation; when the cache memory 11 is hit, the start indication is delayed and after the corresponding bit of the cache memory 11 is made ineffective, the start indication is sent to the processor. In this case, the start indication from the main storage device 14 is delayed behind a start indication at other read time only when the storage device is accessed by the test-and-set operation or only when the cache memory 11 is hit.
Inventors:
Yasutomo Sakurai
Kiyoshi Sudo
Tatsuya Yamaguchi
Koichi Odawara
Takumi Nonaka
Kenji Hoshi
Eiji Kanaya
Kiyoshi Sudo
Tatsuya Yamaguchi
Koichi Odawara
Takumi Nonaka
Kenji Hoshi
Eiji Kanaya
Application Number:
JP16756793A
Publication Date:
February 04, 2003
Filing Date:
July 07, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/00; G06F9/52; G06F12/08; G06F15/16; G06F15/177; (IPC1-7): G06F15/177; G06F12/00; G06F12/08; G06F15/16
Domestic Patent References:
| JP1128156A | ||||
| JP218643A | ||||
| JP638849A | ||||
| JP4181460A | ||||
| JP3149636A | ||||
| JP1126758A | ||||
| JP196746A | ||||
| JP62298866A |
Attorney, Agent or Firm:
Akira Yamatani (1 person outside)