PURPOSE: To accelerate the execution cycle of an instruction by computing a jump address and executing the instruction stored in a second microinstruction register when it is judged that the instruction of the second microinstruction register is an unconditional jump instruction.

CONSTITUTION: When it is judged that the instruction stored in the second microinstruction register 2 is the unconditional jump instruction, it is decoded with a jump instruction judging decoder 4, and furthermore, the jump address of it is computer with a second address arithmetic circuit 9, and it is sent to a first address line 10 via a first address circuit 12, and simultaneously, the instruction stored in the second microinstruction register 2 is executed. Thereby, a fast processor can be realized.