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Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JPH0644104
Kind Code:
A
Abstract:

PURPOSE: To improve debug work efficiency by controlling a system so that a holding means holds data from one device to the other device when the clock of the other device stops.

CONSTITUTION: When a data request device 1 receives a clock stop request in the waiting state of input data 103, it is reported to a control circuit 5 that the clock is to be stopped by a clock report 104, and the clock is stopped at subsequent timing. When the control circuit 5 receives the report, it controls a buffer 4 by a buffer control signal 105 so that transfer data 101 transmitted from a data transmission device 2 is to be stored in response to a data transfer request 100. When data 101 is stored in the buffer 4, the effect is reported to a selection circuit 3 through a control signal 106. The selection circuit 3 switches control so that data 102 in the buffer 4 is selected as input data for the data request device.


Inventors:
MIYAGAWA KOUJI
Application Number:
JP21635092A
Publication Date:
February 18, 1994
Filing Date:
July 22, 1992
Export Citation:
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Assignee:
KOFU NIPPON DENKI KK
International Classes:
G06F11/34; G06F13/38; (IPC1-7): G06F11/34; G06F13/38
Attorney, Agent or Firm:
Yanagi Kawa Shin



 
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