Title:
INITIAL STATE SETTING SYSTEM OF SYNCHRONIZING RECEIVER
Document Type and Number:
Japanese Patent JPS5775301
Kind Code:
A
Abstract:
PURPOSE:To prevent the erroneous control, by converting the output of a potentiometer into digital signals through a subtracting counter and then feeding these signals back to a multirotation synchronizing receiver via a converter. CONSTITUTION:In the preparation state, a digital computer CPU transmits the driving signal to a relay RL. Thus the relay RL works to apply the output of a subtracting counter CT to a converter CV via a contact rl2. At the same time, the output of a code generator CG is applied to the counter CT. Then the value which is shown by the code generated from the generator CG is preset to the counter CT. In this case, if no coincidence is obtained between both input voltages of a comparator CP, the output of the counter CT is set at ''H''. As a result, the clock pulse CLK is applied to the counter CT via an AND gate G, and accordingly the counter CT starts the subtracting count to the preset value.
Inventors:
SATOU MITSUSHIGE
Application Number:
JP15008680A
Publication Date:
May 11, 1982
Filing Date:
October 28, 1980
Export Citation:
Assignee:
HITACHI ELECTRONICS
International Classes:
G05B9/02; G06F11/00; (IPC1-7): G05B9/02