PURPOSE: To expand the range of an operationable power voltage by decreasing a resistance toward a reference level from an output terminal when a power voltage is high and decreasing the resistance toward the power voltage side from the output terminal when the power voltage is low so as to vary the logic decision level.

CONSTITUTION: A P-channel transistor(TR) 8 and N-channel TRs Q1-Qn form a constant voltage supply circuit, and P-channel TRs 9, 10 and an N-channel TR 11 form a voltage detection circuit. While a Vcc is higher than an optional voltage, the relation of Va=VCC exists, and since a P-channel TR 5 controlling the parallel state of a CMOS inverter is turned off and an N-channel TR 6 is turned on, the resistance at the conduction toward the reference level from an output 16 of the CMOS inverter is decreased and the logical decision level is lowered. On the other hand, while the VCC is lower than an optional voltage, since the Va reaches the reference level, the P-channel TR 5 is turned on and the N-channel TR 6 is turned off, and the resistance at conduction toward the power voltage side from the output 16 is decreased and the logic decision level is increased.