PURPOSE: To absorb a phase difference between channels and to synchronize data by obtaining a delay stage number in response to a count of a counter when a frame pulse is generated and delaying and outputting an input data by a set stage number.

CONSTITUTION: The relation between the count of a counter 41 and the number of stages of shift registers 11-13 is stored in a memory 51 in advance. For example, when a signal representing the head of a frame is generated, a counter 41 monitors a time from the time till the occurrence time of frame pulses FP1-3 representing the head of input data DATA 1-3 by counting a clock pulse. The count value when a prescribed frame pulse is generated is used for a read address of the memory 51 and the delay number of stages in response to the count value is read out of the memory and inputted to a delay stage number setting section 61 and set to the relevant shift registers 11-13. Each of the shift registers 11-13 delays the data DATA 1-3 by the set stage number and the data DATA 1'-3' whose phases are phase-locked are outputted.