Title:
INPUT DISCRIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JP3299387
Kind Code:
B2
Abstract:
PURPOSE: To hardly receive influence by an input threshold voltage fluctuation by the manufacture process of a circuit element and to reduce a through-current in an input circuit accompanying the reduction of the number of the input circuits.
CONSTITUTION: This input discrimination circuit is provided with a first output terminal (signal SO) connected to a buffer 1 for outputting binary signals corresponding to the logical level of the binary signals inputted through an input pin, a signal rise detection circuit 2 for detecting the transition of the binary signals outputted from the butter 1 when S1 input valid signals are impressed and generating the binary signals which shift corresponding to rise transition and a latch circuit 24 for outputting the signals through a second output terminal (signal S1) and maintaining already generated binary signal output when the S1 input valid signals are not impressed.
Inventors:
Nishimori Rie
Application Number:
JP14790394A
Publication Date:
July 08, 2002
Filing Date:
June 29, 1994
Export Citation:
Assignee:
Mitsubishi Electric System LSI Design Co., Ltd.
Mitsubishi Electric Corporation
Mitsubishi Electric Corporation
International Classes:
H03K17/00; H03K5/1532; H03K17/16; H03K17/30; H03M5/14; H04L25/49; (IPC1-7): H03K17/30; H03K5/1532; H03M5/14; H04L25/49
Domestic Patent References:
| JP1215113A | ||||
| JP444416A | ||||
| JP6365711A | ||||
| JP1260915A | ||||
| JP194732A |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)