Title:
INPUT OVERVOLTAGE PROTECTION CIRCUIT FOR LOW-POWER CIRCUIT, AND LOW-POWER CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2022067396
Kind Code:
A
Abstract:
To provide an input overvoltage protection circuit for a low-power circuit, in which, even when a fluctuation of an input voltage to a step-up circuit is large, the voltage is restricted, and then, consumption current for protecting the input voltage is minimized, and provide a low-power circuit device.SOLUTION: In a low-power circuit device 201, an input overvoltage protection circuit 101 for a low-power circuit includes a voltage input unit Pi to which an output voltage of a power generation circuit 10 is inputted, a step-up circuit 30 that boosts the voltage of the voltage input unit, and supplies a power source voltage to a latter stage circuit 40, and an overvoltage protection circuit formed of a depletion type FET Q1 between the voltage input unit and the step-up circuit. A drain D of the FET is connected to the voltage input unit. A source S of the FET is connected to an input unit of the step-up circuit. A gate G of the FET is connected to a potential having a reverse bias voltage with respect to that of the source.SELECTED DRAWING: Figure 1
Inventors:
NODA RYUZO
FUJIWARA TERUO
FUJIWARA TERUO
Application Number:
JP2020176086A
Publication Date:
May 06, 2022
Filing Date:
October 20, 2020
Export Citation:
Assignee:
SHO ENG CO LTD
CDN CORP
CDN CORP
International Classes:
H02H9/04
Attorney, Agent or Firm:
Kaede International Patent Office