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Patent Searching and Data


Title:
INPUT STATE MEMORY CIRCUIT USING RELAY
Document Type and Number:
Japanese Patent JPH02183156
Kind Code:
A
Abstract:

PURPOSE: To enable the maintaining of a stable condition free from the elapsing of time by obtaining a state signal corresponding to condition of a memory circuit from a contact connection of a latching type relay.

CONSTITUTION: This circuit is provided with a memory circuit, a state of which changes each time an external signal is received and a data of a specified state is preset according to the closing of a power source or the return thereof and a latching type relay with a connection state switched according to the state of the memory circuit. The memory circuit therein used is, for example, an FF 3 and a latching relay 5 is provided which works corresponding to a state of the FF 3 and the updating of the state of an output signal of the relay 5 is performed with a switching of a memory state of the FF 3. A state signal corresponding to the switching state is held with the relay 5 while being fed to the FF 3 and this holding state is supplied as preset date of the FF 3. This enables the holding of a state corresponding to a change in the memory state of the FF 3 simultaneously.


Inventors:
NISHIZUKA KEN
Application Number:
JP261689A
Publication Date:
July 17, 1990
Filing Date:
January 09, 1989
Export Citation:
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Assignee:
HITACHI CONSTRUCTION MACHINERY
International Classes:
G01D21/00; G01N29/22; G01N29/30; G01N29/44; (IPC1-7): G01D21/00; G01N29/22
Attorney, Agent or Firm:
Kajiyama Bozen (1 person outside)