To minimize a phase difference between an outside clock signal and an inside clock signal, and to reduce power consumption.

This circuit is provided with a clock buffer 10 for generating an inside clock signal PCLK-1 obtained by delaying an outside clock signal CLK, a frequency divider 12 for generating a PCLK-2 by frequency-dividing the PCLK-1, and a main delay 14 for generating a clock signal DCLK-1 by delaying the PCLK-2. The DCLK-1 is supplied to serially connected unit delays 16-1-16-m, and the outputs are respectively inputted to phase detectors 20-1-n, and compared with the PCLK-2. The PCLK-1 is supplied to serially connected unit delays 18-1-m, and DCLK2'-n' are generated. The outputs of the PCLK-1 and the DCLK2'-n' are connected through the phase detectors 20-1-20-n and SW1-SWn. The phase detectors enable-operate the SW1-n according to the synchronizing states of the PCLK-2 and the DCLK.