Title:
INSPECTION METHOD FOR SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JP2004128391
Kind Code:
A
Abstract:
To provide a method for inspecting a semiconductor wafer by which an accurate inspection is possible.
In a step S11, a virtual divided wafer 20 is produced based on a dividing cell size data D1 and a dividing cell arrangement data D2 providing a dividing condition. In a step S12, by checking an inspection result information data base D3 on the virtual divided wafer 20, the number of out-of-standard cells C0 containing out-of-standard parts and the number of standard cells C1 not containing substandard part are calculated, respectively. In a step S13, based on the number of total virtual divided unit cells C10 and the number of standard cells C1, a percentage of usable area PUA (%) (=(C1/C10)*100) is determined.
Inventors:
NARUOKA HIDEKI
Application Number:
JP2002293613A
Publication Date:
April 22, 2004
Filing Date:
October 07, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/66; G01N21/95; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita