Title:
非順序プロセッサのための命令検索及びポート割り当て(FIAP)回路とその方法
Document Type and Number:
Japanese Patent JP4405095
Kind Code:
B2
Abstract:
A find-instructions-and-allocate-ports (FIAP) circuit and method are provided for quickly and efficiently locating one or more instructions that are ready for execution during a launch cycle in an out of order processor and allocating one or more ports associated with one or more execution resources to such ready instructions during the launch cycle. In architecture, the processor includes an instruction reordering mechanism, for example, a queue, having a plurality of slots for temporarily storing a plurality of respective instructions. Instructions can be executed in an out of order sequence from the queue. Each slot is provided with the FIAP circuit for causing and preventing launching, when appropriate, of their respective instruction. A plurality of signals is propagated successively through the FIAP circuits of the queue that causes the queue to launch a predefined plurality of the instructions, which corresponds to a predefined plurality of ports associated with the one or more execution resources. As propagation of the set of signals occurs through each slot, the set of signals indicates to the slot when and which of the one or more ports are available for each said instruction and when none of the ports are available.
Inventors:
Samuel Dee Nafziger
Application Number:
JP2001023626A
Publication Date:
January 27, 2010
Filing Date:
January 31, 2001
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F9/38; G06F9/30
Domestic Patent References:
| JP10260832A | ||||
| JP1194031A |
Attorney, Agent or Firm:
Satoshi Furuya
Kaoru Furuya
Takahiko Mizobe
Kaoru Furuya
Takahiko Mizobe