PURPOSE: To realize a high-speed processing when a branch instruction exists in a branch destination by making an ordinary instruction buffer and a branch destination instruction buffer to be the same constitution, providing a flag showing which is the ordinary instruction buffer and inverting the flag when a branch condition is satisfied, thereby alternately storing the instructions.
CONSTITUTION: The ordinary instruction buffer and the branch destination instruction buffer are made to be the same constitution, and the flag 1 showing which is the ordinary instruction buffer between the instruction buffer 10a and 10b is provided. When the branch instruction is executed and the branch condition is satisfied, the flag 1 is inverted and an ordinary prefetch instruction or the instruction by a preceding branch processing are alternately stored in the instruction buffers 10a and 10b. Thus, an instruction prefetch circuit where the processing speed of a computer is not decreased without increasing hardware quantity even if the branch instruction exists again in the branch destination can be obtained.
NODA TAKAHITO
KAMISAKA YUJI
NONOMURA KAZUYASU
WATABE TORU
TAKENO TAKUMI
KATO SHINYA
POONSHIYAI CHIYONSUWANNAPAISAA
