PURPOSE: To enlarge electrostatic destruction resistance, and to contrive to enhance reliability of the titled device by a method wherein an SSS element is connected electically between the source and the gate of a transistor element, while the SSS element is formed on one main face of a semiconductor substrate common with the transistor element.

CONSTITUTION: P-N-P-N junction is constructed between various regions of an N type region 4, P type regions 5∼7 of the three places formed extending over the center of the N type region 4 and a substrate, N+ type regions 8∼10 of high impurity concentration formed in the P type regions 5∼7, etc., formed to the semiconductor substrate 3 according to the diffusion method to form the SSS element. An Al electrode 11 adhered on the P type regions 5, 7 and the N+ type regions 8, 10 is connected to the source S of the transistor element Tr. Moreover, an Al electrode 12 adhered on the P type region 6 and the N+ type region 9 at the center is connected to the gate electrode G1 or G2 of the transistor element Tr.