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Title:
INSULATED GATE TYPE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH05283706
Kind Code:
A
Abstract:

PURPOSE: To expand the effective area of a semiconductor substrate and to reduce ON-resistance by a method wherein a source bonding pad region, which is used common with a unit cell, is provided in advance on one surface of a semiconductor substrate, and a plurality of unit cell regions and a prober region, having the area two or three times the unit cell region, are provided on the part directly under the source bonding pad region.

CONSTITUTION: A plurality of unit cell regions 8 and a P+ diffusion region 9, having the area two to three times the unit cell region 8, are formed on the semiconductor substrate located directly under a source bonding pad region which is provided in advance. A part of the source bonding pad is used as a P+ prober region and other part is used as an effective part which works as a MOSFET. The P+ area is formed larger than a flaw caused by a probing needle, and the wafer damage, caused when current and voltage between the source and drain are tested in the manufacturing process by bringing a probing needle into contact with an electrode part to check and select the characteristics of each cell and the like in a diffusion process and the like, is prevented.


Inventors:
Wataru Toshige
Application Number:
JP10365892A
Publication Date:
October 29, 1993
Filing Date:
March 30, 1992
Export Citation:
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Assignee:
Shindengen Industry Co., Ltd.
International Classes:
H01L21/60; H01L29/78; H01L29/417; (IPC1-7): H01L29/784; H01L21/60



 
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