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Title:
INSULATED GATE TYPE FIELD EFFECTIVE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5834975
Kind Code:
A
Abstract:

PURPOSE: To produce a complementary FET having different threshold voltages of identical conductivity type without calling for any additional manufacturing process by forming a gate electrode of polycrystalline silicon consisting of one conductivity type and reverse conductivity type regions.

CONSTITUTION: For a P type channel transistor, a gate electrode is of P type polycrystalline silicon 21 at the ends of a source and drain, and of N type polycrystalline silicon 22 in the middle. Therefore, a P-N junction is produced in the gate electrode so that holes 17 can be formed through both the P type polycrystalline silicon 21 and the N type polycrystalline silicon 22 to connect them together through metal 18. It is found that three transistors M1∼M3 are connected in series according to the equivalent electric circuit of the transistors. The threshold voltage becomes the same as that of the transistor M2 so that higher threshold voltage can normally be maintained than P type channel transistors.


Inventors:
HOSHI TOSHIAKI
Application Number:
JP13527381A
Publication Date:
March 01, 1983
Filing Date:
August 27, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L27/08
Attorney, Agent or Firm:
Uchihara Shin



 
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