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Patent Searching and Data


Title:
INSULATED GATE TYPE TRANSISTOR
Document Type and Number:
Japanese Patent JPS6251263
Kind Code:
A
Abstract:

PURPOSE: To reduce parasitic capacitance between a gate and a drain, to prevent a short channel effect and a hot electron effect and to suppress punch-through between a source and the drain, by providing a low concentration region having the reverse conducting type with respect to a substrate at the side wall part of a gate insulating film.

CONSTITUTION: On a one-conducting type semiconductor substrate 1, first semiconductor layers 4 and 5 including low concentration impurities having the reverse conducting type are laminated. The first semiconductor layers 4 and 5 are selectively removed, and a groove part is formed. An insulating gate film 9 is embedded in the groove part. Said first semiconductor layers 4 and 5 are made to remain at a part, where the side wall of the gate 9 is in contact with an insulating film 8. At the other part around the layers, second semiconductor layers 6 and 7, which have the same conducting type with respect to the semiconductor 1 and have the impurity concentration higher than that of the substrate 1, are formed at deeper positions. Third semiconductor layers 2 and 3, which have the reverse conducting type with respect to the semiconductor substrate 1 and include high concentration impurities, are formed at upper shallow positions on the layers 6 and 7. Said third semiconductor layers 2 and 3, which are isolated by the insulating gate 9, are made to be a source and a drain. Thus a depletion layer, which is extended on the drain and the substrate, is suppressed. Punch-through is hard to occur even in a minute element.


Inventors:
KONAKA MASAMIZU
Application Number:
JP18971085A
Publication Date:
March 05, 1987
Filing Date:
August 30, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/78; (IPC1-7): H01L29/60; H01L29/78
Attorney, Agent or Firm:
Noriyuki Noriyuki