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Title:
INSULATING GATE TYPE FIELD EFFECT TRANSISTOR AND ITS PREPARATION
Document Type and Number:
Japanese Patent JPS5582468
Kind Code:
A
Abstract:

PURPOSE: To accurately control the width of a channel region, and to improve yield, by separating a portion between a source and a drain of a double diffusion type IG-FET by means of a groove, and by mounting a gate electrode into the groove through an insulating layer.

CONSTITUTION: A p-type channel dope region 2 is formed by selectively diffusing p-type impurities to a p-type semiconductor substrate 1 with low concentration from a window 5 of an oxide film mask 6. An n+-type region 7, which is shallower than the p-type region 2 and which one portion stacks to the region 2, is selectively made up by using the other oxide film mask. The n+-type region 7 is divided into two independent regions 3, 4 by etching the substrate in an aeolotropic shape from a window 8 of the oxide film 6' again built up, and a concave portion 9 is formed so that the channel dope region 2 be exposed. A gate electrode G is mounted to the concave portion 9 through a gate insulating film 10, and a source electrode S and a drain electrode D are installed to the n+-type regions 3, 4. Thus, the width of the channel can precisely be controlled.


Inventors:
TANIGAWA YOSHIKI
HIRASHIMA KUNIHIKO
Application Number:
JP15709778A
Publication Date:
June 21, 1980
Filing Date:
December 14, 1978
Export Citation:
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Assignee:
PIONEER ELECTRONIC CORP
International Classes:
H01L29/78; H01L29/10; H01L29/417; H01L29/423; (IPC1-7): H01L29/06; H01L29/60; H01L29/78



 
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