Title:
A/D CONVERTER
Document Type and Number:
Japanese Patent JP3221131
Kind Code:
B2
Abstract:
PURPOSE: To realize the A/D converter circuit in which high speed conversion processing is attained, the chip area is decreased and the power consumption is reduced.
CONSTITUTION: The A/D converter circuit is provided with plural switching blocks S11-S47 detecting the presence of low-order bit data and redundant bit data for each prescribed string, a high-order encoder comparing a predetermined reference voltage with an input signal and obtaining a high-order bit conversion code in response to a redundant mode or a non-redundant mode depending on the result of comparison, a low-order encoder 110 obtaining a conversion code in a low-order bit from an output of each switching block and a conversion code in a redundant bit at the outside of a conversion range of the high-order encoder and generating a selection signal in response to the redundant mode and the non-redundant mode depending on the presence of the redundant bit data, a selection gate 120 to provide selectively an output of the conversion code in high-order bits in response to the redundant mode and the non-redundant mode based on the selection signal outputted from the low-order encoder among conversion codes of the high-order bits in response to the redundant mode and the non-redundant mode.
Inventors:
Kunihiko Izuhara
Application Number:
JP3324093A
Publication Date:
October 22, 2001
Filing Date:
February 23, 1993
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03M1/14; H03M1/36; (IPC1-7): H03M1/14; H03M1/36
Domestic Patent References:
| JP1190029A | ||||
| JP2123829A | ||||
| JP2125530A | ||||
| JP2126725A | ||||
| JP2128524A | ||||
| JP2141028A | ||||
| JP2132920A | ||||
| JP2137420A | ||||
| JP2202224A | ||||
| JP4196923A | ||||
| JP63299615A | ||||
| JP277931U |
Attorney, Agent or Firm:
Takahisa Sato