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Patent Searching and Data


Title:
INTEGRATED CIRCUIT DEVICE OF SEMICONDUCTORS
Document Type and Number:
Japanese Patent JPH04168381
Kind Code:
A
Abstract:

PURPOSE: To enable decrement of the number of constituent elements by constituting a scan register of master slaves F/F and ratches which are connected alternatively.

CONSTITUTION: At a device that enable testing by a scanning method, a plurality of scan registers corresponding to the bit number of propagating data, are provided for each part among a plurality of circuit blocks. In the case of ordinary operation or testing operation, output data of the forestage block as it is, or, the data or test data synchronized and held by an external clock, are output, in accordance with each the operational condition. In this way, a shift register bus is connected so as to obtain one single register function, as a whole. In this case, the shift register circuit is constituted of a master slave F/F 2 operated by not-duplicated clocks T1 and T2, and an ordinary ratch 1 operated by a clock T, both of which are connected alternatively. Consequently, since in an N-bit shift register circuit constitution, the ratch 1 can cover N/2 bit part, and therefore the number of elements can be decreased.


Inventors:
HAYAKAWA YASUSHI
Application Number:
JP29636390A
Publication Date:
June 16, 1992
Filing Date:
October 31, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/22; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)