Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5858741
Kind Code:
A
Abstract:
PURPOSE:To facilitate arrangement by a method wherein the regularity of the arrangement positions of contact holes is maintained by increasing the degree of freedom for wiring. CONSTITUTION:A P well 2,a P<+> source and drain region 3, an N<+> source and drain region 4, an N<+> layer 5 for voltage application and a P<+> layer 6 for voltage application are provided on a semiconductor substrate 1. Contact holes formed in polysilicon layers 8d-8j, for example 9h1, 9h2 are formed on (y) lattices 10a1, 10a4 and two (y) lattices 10a2, 10a3 are provided between the (y) lattices 10a1, 10a4. The layers 8d, 8f are the input gate electrodes of a P-MOSFET having a region 3 and the layers 8h, 8j are the input gate electrodes of an N- MOSFET having a region 4. The contacts 9b of the region 3 are located on the (y) lattices 10a6, 10a9 and one (y) lattice 10a5 or 10a10 is provided between the contact holes 9h4 or 9h5.
Inventors:
FUJIKI KUNIMITSU
Application Number:
JP15839181A
Publication Date:
April 07, 1983
Filing Date:
October 05, 1981
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/118; H01L29/41; (IPC1-7): H01L27/04
Domestic Patent References:
| JPS5582448A | 1980-06-21 | |||
| JPS5582449A | 1980-06-21 | |||
| JPS5582450A | 1980-06-21 |
Attorney, Agent or Firm:
Uchihara Shin