Title:
集積回路装置およびローカル読出/書込回路
Document Type and Number:
Japanese Patent JP4246454
Kind Code:
B2
Abstract:
A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory ("DRAM") arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable ("RWEN") or separate read enable ("REN") and write enable ("WEN") signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.
More Like This:
| JPH0240194 | SEMICONDUCTOR MEMORY |
| JP2555900 | [Title of Invention] Output control circuit of semiconductor memory |
| JPH11306758 | SEMICONDUCTOR STORAGE |
Inventors:
Michael sey paris
Kim She Hardy
Kim She Hardy
Application Number:
JP2002240622A
Publication Date:
April 02, 2009
Filing Date:
August 21, 2002
Export Citation:
Assignee:
ユナイテッド・メモリーズ・インコーポレーテッド
ソニー株式会社
ソニー株式会社
International Classes:
G11C11/409; G11C11/4096; G11C7/10; G11C11/407; G11C11/4093
Domestic Patent References:
| JP2000243086A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai