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Title:
INTEGRATED CIRCUIT FOR FUZZY LOGIC ARITHMETIC
Document Type and Number:
Japanese Patent JPH03113537
Kind Code:
A
Abstract:

PURPOSE: To freely form a fuzzy logic arithmetic by leading a fuzzy logic arithmetic output signal out of an external terminal of a MAX circuit.

CONSTITUTION: A MIN output signal line LO1 is provided to lead the output voltage y1 - ym of each MIN circuit 21 in a semiconductor chip 10. At the same time, a MAX input signal line LI2 is connected to three input terminals of each MAX circuit 31 forming a MAX circuit array. All lines LO1 are connected to all lines LI2 via the micro-fuses 39. The lines LI2 are connected to a terminal 14 connected to the ground via a resistor R3 at an end part opposite to the input terminal of the circuit 31. In such a constitution, the MIN and MAX serving as the basic logics for a fuzzy logic arithmetic can be optionally combined for execution of operations.


Inventors:
TERAMOTO HIROSHI
Application Number:
JP25062489A
Publication Date:
May 14, 1991
Filing Date:
September 28, 1989
Export Citation:
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Assignee:
JAPAN RES DEV CORP
YAMAKAWA RETSU
OMRON TATEISI ELECTRONICS CO
International Classes:
G05B13/02; G06F9/44; G06N7/02; (IPC1-7): G05B13/02; G06F9/44
Attorney, Agent or Firm:
Kenji Ushiku