Title:
INTEGRATED CIRCUIT HAVING COMBINED LOGIC FUNCTION HAVING TRANSFER GATE HAVING LOW THRESHOLD VOLTAGE
Document Type and Number:
Japanese Patent JPH0217714
Kind Code:
A
Abstract:
PURPOSE: To improve the reliability of an operation with high switching frequencies by making the threshold voltage of a transistor in a transfer gate lower than the threshold voltage of a transistor in a sub-circuit connected with the transfer gate. CONSTITUTION: A multiplex circuit is provided with an inverter circuit including a pMOS transistor P1 and an nMOS transistor N1, and two transfer gates formed of nMOS transistors T1 and T2. A rate between the threshold voltages of the transistors T1 and T2 in the transfer gate and the threshold value in the inverter circuit is set equal to about 0.6 or less.
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Inventors:
BAATO JIYOSEFU SUZANNU DE ROOR
Application Number:
JP10331389A
Publication Date:
January 22, 1990
Filing Date:
April 21, 1989
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H03K17/30; H03K3/356; H03K17/693; H03K19/0185; H03K19/096; (IPC1-7): H03K17/30; H03K17/693; H03K19/00; H03K19/0185; H03K19/096
Domestic Patent References:
| JP62502370Y |
Foreign References:
| US4250406A | 1981-02-10 | |||
| US4595845A | 1986-06-17 |
Attorney, Agent or Firm:
Masao Sawada
Next Patent: JPH0217715