Title:
INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3953981
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To increase the degree of vertical separation between a passing wordline and a strap.
SOLUTION: If the thickness of an insulation layer is decreased in an SOI integrated circuit including a trench capacitor DRAM array, crosstalk is caused between a trench capacitor and the passing wordline 214 which passes over the trench capacitor. The buried strap on a capacitor center electrode 105 is enabled to come into contact with the backside of an SOI layer 60 by increasing the depth of a recess at the upper part of the trench and laterally undercutting the insulating layer, thereby increasing the degree of vertical separation between the passing wordline 214 and the strap.
Inventors:
Jack A. Mandelman
Herbert El Ho
Herbert El Ho
Application Number:
JP2003151411A
Publication Date:
August 08, 2007
Filing Date:
May 28, 2003
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/8242; H01L21/334; H01L21/84; H01L27/108; H01L27/12; H01L29/76; H01L29/94; H01L31/119; (IPC1-7): H01L21/8242; H01L27/108
Domestic Patent References:
| JP9027599A | ||||
| JP2002033484A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno
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