Title:
INTEGRATED CIRCUIT TESTING METHOD AND APPARATUS
Document Type and Number:
Japanese Patent JPS55149063
Kind Code:
A
Abstract:
In order to set the circuit to be tested to a test mode, at least one output is led out by an output stage, and the input and output of the output stage internally leads to an exclusive-OR gate. As long as the output has a comparatively high-ohmic termination, as is the case during the normal mode of operation, the exclusive-OR gate will carry the same signal for both signal conditions of the output. For the purpose of testing a complementary pulse pattern is applied to the output, so that the exclusive-OR gate supplies an opposite signal, which establishes the test mode. The output of the exclusive-OR gate may lead to a bistable multivibrator, so that for establishing the test mode only a single complementary signal is required.
Inventors:
YOZEFUSU DERUBINIYU
Application Number:
JP5491380A
Publication Date:
November 20, 1980
Filing Date:
April 26, 1980
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G01R31/317; G01R31/3185; G01R31/28; (IPC1-7): G01R31/26