INTEGRATED CIRCUIT WITH SELECTABLE GATE THICKNESS AND METHOD OF MANUFACTURING THE SAME

Title:

INTEGRATED CIRCUIT WITH SELECTABLE GATE THICKNESS AND METHOD OF MANUFACTURING THE SAME

Document Type and Number:

Japanese Patent JP2003197557

Kind Code:

A

Abstract:

To provide a method capable of locally adjusting the thickness of a layer in semiconductor processing, which can improve evenness, reproducibility of the layer, and cost performance.

The method for obtaining layers which have different thickness or height of the layer, and are manufactured using a same device material is disclosed. A specific example of such a process is a CMOS process comprising nMOS and pMOS having a different gate electrode thickness. After forming the device material layer or gate electrode layer 2, disposable parts 4 are formed in selected regions 3 of the device layer 2. Preferably, the disposable parts are formed with doping the selected regions 3 to a required depth d. A film thickness t of the device layer 2 as-deposited is adjusted or modulated after the patterning of respective devices by removing the disposable regions 4.

Inventors:

JURCZAK MALGORZATA
ROOYACKERS RITA
AUGENDRE EMMANUEL
BADENES GONCAL

Application Number:

JP2002310793A

Publication Date:

July 11, 2003

Filing Date:

October 25, 2002

Export Citation:

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Assignee:

IMEC INTER UNI MICRO ELECTR

International Classes:

H01L21/28; H01L21/3215; H01L21/8238; H01L27/092; (IPC1-7): H01L21/28; H01L21/8238; H01L27/092

Domestic Patent References:

JP2001007222A	2001-01-12
JP2000058868A	2000-02-25

Attorney, Agent or Firm:

Aoyama Ryo (1 person outside)

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