Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3461571
Kind Code:
B2
Abstract:
PURPOSE: To simply construct resistor stages, put each of the resistor stages in quick operation and enable a simple and reliable test mode.
CONSTITUTION: When a test signal pattern is loaded and read out, a multiplexer 14 receives the first selection signal at a line 26 and connects a line 17 to a line 15. In normal operation, a signal value is always supplied to the clock input of a level clock memory stage 12 for switching to a transparent operation.
Inventors:
Kurt Shoreman
Harald Abelt
Harald Abelt
Application Number:
JP12249394A
Publication Date:
October 27, 2003
Filing Date:
June 03, 1994
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G01R31/3185; G01R31/28; G06F11/26; H01L21/66; (IPC1-7): G01R31/28
Domestic Patent References:
| JP5160682A | ||||
| JP58225365A | ||||
| JP2300826A |
Attorney, Agent or Firm:
Kosugi Sugimura (4 others)