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Patent Searching and Data


Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6025462
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of terminals without requiring any other test terminal by connecting a field effect transistor (FET) which has a floating gate to a terminal for normal operation.

CONSTITUTION: Signals inputted to terminals 1 and 2 of an integrated circuit L which is a one-chip microcomputer are supplied to input circuits 3 and 9 which serve as a buffer through lines 10 and 11 and are used for the arithmetic operation of the microcomputer. When the integrated circuit L is placed in test mode, a voltage having a larger absolute value than a normal operating voltage is applied between the terminals 1 and 2. Consequently, a change is injected into the FET5, which turns on, so that the voltage at a connection point 12 exceeds the threshold value of a level discriminating circuit 7. Therefore, a line 14 goes up to a high level and the integrated circuit L performs predetermined operation in test mode.


Inventors:
MURAMATSU TOSHIHIKO
ISHITSUKI NORIYOSHI
SUMIYA SHINJI
Application Number:
JP13498483A
Publication Date:
February 08, 1985
Filing Date:
July 22, 1983
Export Citation:
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Assignee:
SHARP KK
International Classes:
G01R31/317; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Keiichiro Saikyo