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Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS61194761
Kind Code:
A
Abstract:

PURPOSE: To prevent an excess undershoot on a grounding line, and to obviate the increase of the retardation time of an adjacent output circuit due to the augmentation of the number of simultaneous ON output circuits by connecting an output from a current amplification circuit, to the input of which an output from a reference-voltage generating circuit is connected, with the grounding line in which the undershoot is generated by simultaneous ON operation.

CONSTITUTION: In a clamping circuit 10, currents are fed to a grounding line GND when the undershoot of the grounding line GND lowers to some value or less by properly setting the value of the output potential VREF of a reference- voltage generating circuit RVC, thus preventing the excess undershoot of the grounding line GND. Since the output potential of the reference-voltage generating circuit can be set arbitrarily by devising circuit constitution thereof, permissible undershoot levels are estimated in each case of several integrated circuit, and the reference-voltage generating circuits corresponding to the values can be designed. Accordingly, the increase of the retardation time tPLH of adjacent output circuits resulting from excess undershoots can be obviated, thus improving the retardation time of ICs.


Inventors:
KIYOZUKA NOBORU
Application Number:
JP3381285A
Publication Date:
August 29, 1986
Filing Date:
February 22, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/04; G05F1/46; H01L21/822; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Uchihara Shin



 
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